WP3 IP Platform

The objective of Work Package 3 is to act as IP factory to build up necessary hard (fixed technology node) and soft (re-targetable digital designs) sub-components (IP) for the requirements of the designed components in Work Package 4. It clusters all of the soft and hard IP/PHY design activities to leverage synergies between partners, which are working towards providing generic or dedicated and self-contained “Lego” building blocks. At project level the common system requirements are analyzed at demonstrator level (WP5) and broken down into component requirements in WP4. Therefore, WP3 focuses on the circuit design, verification, manufacturing and validation effort to generate from the ground up the necessary advanced IPs in various FD-SOI technology flavors (28nm, 22FDX, 12FDX) in order to enable realization of key features implemented into the components (SoCs and High End Microcontroller) in WP4.
This work package is divided into 5 tasks: At the same time the design methodology and automation are addressed in a separate task (Task 3.5) in order to boost the synergies in productivity improvement towards 28nm/22FDX/12FDX FD-SOI circuit and component design and migration. The developed IPs aim to facilitate and accelerate the development of advanced ASIC and SoC products, aiming autonomous vehicles with HPC, advanced vision/data signal processing, sensor fusion and RF and mm-wave features. Although the IPs are targeted for SoC in the autonomous vehicles, per definition, as a generic IP library, they will improve in general the productivity towards Smart-X domain applications by increasing the number of available building stones available for the FD-SOI technology and ecosystem. The optimal FD-SOI technology node is selected on cost / performance needs of the target application.
Lead FhG-EMFT
Involved Partners :